Thursday, September 17, 2009

Next Generation Jermar

The Next Generation Jermar is called Víťa (short form of Vítězslav) and was born on September 16, 2009 at 3:17 AM.


The picture of Vita and his happy mother. Welcome to our world, Vita!

Thursday, September 10, 2009

Great technical read for clock-cycle tuners

Yesterday I found a great paper by Vlastimil Babka and Petr Tuma, both from Department of Software Engineering Faculty of Mathematics and Physics, Charles University (yes I am feeling very proud of my alma mater now :-). The paper is titled Investigating Cache Parameters of x86 Family Processors and via sophisticated benchmarking and use of hardware performance and event counters provides gory details about the internal structure of contemporary Intel and AMD processors' TLBs and memory caches, including precise estimates of the respective miss penalties in clock cycles. What is so cool about the information provided in the paper is that it is not publicly available from elsewhere (including vendor documentation) and that the estimates are provided for the individual parts that form the TLB and the cache.

Although the paper itself concludes that the presented data is probably too low-level for general software development, I can imagine that for example the L4 people may be interested in using it to update their 1993 paper Improving IPC by Kernel Design with todays clock cycle counts.